In general, a semiconductor device is manufactured by repeatedly performing on a semiconductor wafer various processes such as a film deposition process, a pattern etching process and the like. A demand for increasingly higher degree of integration and miniaturization of semiconductor devices leads to a further miniaturization of a line width or an opening diameter. Further, as for a wiring material or a material to be buried inexpensive Cu (copper) of a small electrical resistance tends to be used due to a miniaturization of various dimensions (see, Japanese Patent Laid-open Application No. 2000-77365). In case Cu is used for the wiring material or the material to be buried a barrier layer thereunder is generally formed of a tantalum metal film, a tantalum nitride film or the like by considering adhesivity and the like.
In order to form the barrier layer, a tantalum nitride film (hereinafter, referred to as “TaN film”) is formed, as an underlying layer, on a wafer top surface and on a surface of a recess opened at the top surface in a plasma sputtering apparatus. Next, a tantalum film (hereinafter, referred to as “Ta film”) is formed on the TaN film in the same plasma sputtering apparatus. Then, a thin seed film formed of a Cu film is formed on a surface of the barrier layer. Thereafter, a Cu plating process is performed on the entire wafer surface (the wafer top surface and the recess surface) thereby filling the recess.
FIG. 8 is a fragmentary vertical cross sectional view showing a peripheral portion of a recess of a semiconductor wafer S on which films have been deposited by employing a general plasma sputtering technique. A recess 2 opened at a top surface of the semiconductor wafer S corresponds to via hole, a through hole, a groove (a trench or a dual damascene structure) or the like. Due to a miniaturization of a design rule, the recess 2 has a considerably large aspect ratio (e.g., about 3 to about 4). For example, a width or an inner diameter of the recess 2 is about 0.01 μm.
Referring to FIG. 8, an underlying layer 4 formed of a TaN film is substantially uniformly formed on the entire surface of the wafer S (the top surface and the surface of the recess 2) in a plasma sputtering apparatus. Further, a metal film 6 formed of a Ta film is formed on the underlying layer 4 in the same plasma sputtering apparatus. When the underlying layer 4 or the metal film 6 is formed in the plasma sputtering apparatus, a high frequency bias power is applied to a mounting table for mounting thereon the wafer S to thereby attract metal ions. Next, a thin seed film formed of a Cu film is formed on an entire surface of the metal film 6 and, then, a Cu plating process is performed thereon, thus filling the recess 2 with the Cu film.
In general, when a film deposition is carried out in a plasma sputtering apparatus, a film deposition rate is increased high by attracting metal ions into a wafer surface by applying a bias power to a mounting table for mounting thereon a semiconductor wafer. However, if a bias power is excessively increased, the wafer surface is made to sputter by a discharge gas, e.g., Ar (argon) gas, introduced into the apparatus to generate a plasma, thereby removing deposited metal films, wherein the discharge gas is such gas that no deposition generate when the discharge gas is activated by plasma. To that end, the bias power is set to a level which is not too large.
In case the metal film formed of a Ta film has been deposited, the metal film 6 is likely to be formed in the recess 2 in a state shown in FIG. 8. In other words, the metal film 6 is adhered to a bottom portion of the recess 2 and to an upper portion of a sidewall of the recess 2 and, also, overhang portions 8 protruding toward an opening of the recess 2 are formed in the metal film 6. Further, bare portions 10 to which the metal film 6 is not deposited may be formed on a lower portion of the sidewall of the recess 2. This is because the metal ions generated by the sputtering have poor directionality and thus collide with the upper portion of the sidewall before they reach the lower portion of the sidewall in the condition that the bias power is not too large. As a consequence, the recess 2 is not completely filled with a Cu film even after a plating treatment or the like has been finished thereby developing a void.